Efficient bit-parallel systolic architecture for multiplication and squaring over GF(2m)
Kee-Won Kim, Seung-Hoon Kim · IEICE Electronics Express · 2017
In this letter, we propose a parallel-in parallel-out systolic array for concurrently computing multiplication and squaring over GF(2m). For m ≥ 400, the proposed bit-parallel systolic array can save about 50% time complexity as compared to the corresponding existing structure. The proposed array can be used as a core circuit for various applications. Also our architecture is well suited to VLSI implementation as well.