14nm Broadwell Xeon® processor family: Design methodologies and optimizations
Mahesh K Kumashikar, Shridhar G Bendi, Srikanth Nimmagadda, Anup J Deka, Anil Agarwal · 2017
This paper provides details on the new Broadwell server product family designed on 14nm Intel process. This was the first Xeon® server product on this process node. Low power, density optimized product, Broadwell-DE, has upto 8 dual-threaded 64b Broadwell cores [1], 12MB L3 cache, 2 10GT/s Ethernet KR lanes, 2 DDR4–2400MHz memory channels and 24 8GT/s PCIe lanes. Broadwell-SP, a high performance server CPU, has upto 24 dualthreaded cores, 60MB L3 cache, 4 DDR4 channels and 48 PCIe lanes. While introducing servers with varying segment types on a lead process node provides business advantages, it entails designs ability to operate across larger window of operation especially on evolving process collaterals. This paper shows a case study of server chips on 14nm process node [2], and methodologies that were used to debug and productize. The paper will show silicon results which support the strength of the methodology.