Accelerated Embedded AKAZE Feature Detection Algorithm on FPGA
Lester Kalms, Khaled Salah Mohamed, Diana Göhringer · 2017
Feature detection is a major operation in various computer vision systems. The KAZE algorithm and its improved version, Accelerated-KAZE (AKAZE), are considered as the first algorithms to detect features by building a scale space using nonlinear diffusion. However, the detection part of the algorithm achieves only 6 fps on an Intel Core i7-4790 processor for an image resolution of 1024x768. This work proposes a pipelined architecture for a hardware accelerator that performs the AKAZE detection algorithm. Firstly, modifications are done to the original algorithm to reduce the amount of computations and memory accesses. Then, the accelerator is implemented on a Xilinx Zynq SoC and achieves 98 fps for the same resolution and a frequency of 100 MHz. Compared to the original algorithm, the design has an error in average inliers ratio by only 4%.