Area efficient modified booth adder based on sklansky adder
Anubhav Garg, Deepak Agrawal, Priyank Kularia, Nidhi Gaur, Anu Mehra, Sachin Kumar Rajput · 2017
In this paper an area optimized 16-bit booth multiplier is proposed. The proposed architecture is based on parallel prefix Sklansky adders. The architecture is also implemented using Carry Look ahead adder, Kogge Stone adder, Ladner-Fischer adder and Brent Kung adder. The adders are compared in terms of LUTs and power. The approach using Sklansky based 16-bit modified Radix-4 booth architecture is found to be 29.31% optimized for area in comparison to Carry Look Ahead adder. The tool for implementation is Xilinx Vivado 4.2 on Artix 7 board on 28 nm technology.