Speed optimization of aes algorithm with hardware-software co-design
Preeti M. Dixit, Jitendra B. Zalke, Sharmik Admane · 2017
In present scenario the FPGA technology has ability to design, efficient and high performance embedded systems which are based on soft core processors, embedded memories and the IP core. In design of such FPGA based systems with softcore processor, to gain and improve the performance, the Hardware-Software Co-design is generally used. Thus the proposed work is based on the study of effect of Hardware-Software Co-design on performance parameter. An AES cryptography algorithm is taken as an application, which is implemented on a soft core processor using Microblaze. AES (Advanced Encryption Standard) is a viable encryption algorithm used in application like Internet applications, RFID devices etc. to provide digital security. Cryptography plays an important role for end-to-end safe communication.