A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices
Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou · 2017
An AES core designed for low-cost and energy-efficient IoT security applications is fabricated in a 65nm CMOS technology. A novel Dual-Rail Flush Logic (DRFL) with switching-independent power profile is used to yield intrinsic resistance against Differential Power Analysis (DPA) attacks with minimum area and energy consumption. Measurement results show that this 0.048mm2core achieves energy consumption as low as 1.25pJ/bit while providing at least 2604x higher DPA resistance over its conventional CMOS counterpart, marking the smallest, most energy-efficient and most secure full-datapath AES core.