A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8–1.0V in 40nm
Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto · 2017
A fully-synthesizable Physically Unclonable Function (PUF) with hysteresis-enhanced stability and active compensation of temperature variations is proposed. In detail, a bitcell based on low-voltage regulated Cascode current mirror is introduced. To reduce undesired bit flips, hysteretic behavior is obtained through the insertion of a Muller C-element output stage, which mitigates the effect of noise, voltage and temperature fluctuations on the PUF output. Measurements in a 40nm test chip show that hysteresis improves the bit error rate (BER) by 14%. A feedback scheme is also introduced to compensate the effect of temperature variations at run time, improving the intra-PUF Hamming distance by 40% and BER by 6-7% under temperature variations (25-85°C). Native worst-case BER of 2.8% is measured under 0.8-1.0V and 25-85°C, with instability degradation with temperature being 0.15% per 10°C. The PUF bitcell consumes 1.02fJ/b at 0.9V, achieving an energy efficiency of 16Tbps/W and maximum throughput of 24Gbps. Also, the proposed PUF can be designed with fully automated standard cell-based flows, thus enabling substantial design effort reduction compared to prior art based on custom design styles.