FPGA implementation technique for power consumption aware tamper resistance accelerator of lightweight PUF
Yoshiya Ikezaki, Yusuke Nozaki, Hideki Nagata, Masaya Yoshikawa · 2017
The semiconductor counterfeiting has become a serious problem. Physical Unclonable Function (PUF) is attracted attention as a countermeasure. PUF can generate a unique ID for each device utilizing a variation during manufacturing. However, PUF is vulnerable to modeling attacks. In addition, it is reported that side-channel information allows modeling attacks effectively. To secure the safety of semiconductors, the evaluation of tamper resistance of PUFs is important. This study proposes an evaluation method for Lightweight PUF on FPGA. The proposed method can analyze the deference of power consumption, which affects tamper resistance. Experiments prove the validity of the proposed method.