Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture
Jian Gong, Yang Mengfei · IEEE Transactions on Evolutionary Computation · 2017
With the continuous development of computer and electronics, the idea of artificial intelligence has been integrating into the fault tolerance research. As a valuable and prospective intelligent fault tolerance technique in high reliability and high safety applications, the evolvable hardware fault tolerance technique is becoming an important and widely applicable method. However, this technique confronts two difficult problems: evolved circuit scale and evolution efficiency. Toward these problems, we present a programmable architecture called neural network architecture-based virtual reconfigurable circuit (NNA-VRC), and an evolutionary fault tolerance method based on this programmable architecture. The NNA-VRC-based evolution method simplifies the structure and configuration of programmable architecture, avoids illegal interconnections during the circuit evolution, and implements high level (module level) evolution. The experiments of this paper show that a function module scale circuit is evolved efficiently. Furthermore, NNA-VRC-based evolution method can recovery from many injected fault patterns, behaving a strong feature of fault tolerance.