High level computation technique for characterization of sigma-delta a/d converter
Anil Kumar Sahu, Vivek Kumar Chandra, Ganesh Ram Sinha · 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS) · 2017
We present in this paper about high level computation technique used in characterization of highresolution Sigma-Delta modulator Analog to digital (ADC) implemented with the help of software and Xilinx hardware EDA tool environment. This paper suggests high level computation of static and dynamic parameters of sigma delta Analog and converter. Novelty of the suggested computation method lies in terms of introduction of Output Response Analyzer (ORA) and on chip test generation being used for testing of ADC parameters that help in reducing the difficulties in design complexity of integrated circuits, such as test stimuli generation(TSG) and CORDIC respectively. Modeling of TSG of analog and Ramp signal are achieved using MATLAB SIMULINK; and CORDIC of histogram based response is modeled using MATLAB in build with SIMSIDES. Moreover, the fault coverage and error in the computation of different parameters of oversampled ADC are also computed in the ORA design of Built-In self-Test (BIST) with less hardware and reduced area overhead. Signal to Noise (SNRd) of sigma delta ADC is found as 103.1 dB.