An area efficient multi-mode memory controller based on dynamic partial reconfiguration
Khaled Salah · 2017
This paper presents an efficient design method used to implement high performance multi-mode memory controllers which fits different applications with different demands. The proposed design method is based on the use of dynamic partial reconfiguration (DPR) to commute from mode to another using time-multiplexing on the same chip region to save considerable area and enable usage of low-cost FPGAs. DPR technique is a promising solution to save area and improve performance. In this work, the multi-mode memory controller consists of three modes of operations: SDRAM mode, NOR flash mode, and NAND flash mode. The DPR is applied between these modes to switch from mode to another. The results shows that the area saving is powerful at the expense of acceptable latency.