A novel implementation of 4-bit carry look-ahead adder
Jia Miao, Shuguo Li · 2017
Carry look-ahead adder (CLA) is a fast adder. This paper is delicated to accelerate the 4-bit CLA circuit. In proposed circuit structure, XOR gate is replaced by NOR gate. Moreover, logic gates have less fan-in and fan-out and signal throughs one less MOS transistor in critical path. All designs are built in dynamic CMOS logic gates. Simulation results show that the proposed architecture has advantages over conventional circuits in speed, area and power consumption.