An efficient hybrid integer coefficient-DCT architecture using quantization module for HEVC standard
Ganapathi Hegde, P. G. Akhil · 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS) · 2017
This work gives an efficient integer coefficient based discrete cosine transform (I-DCT) module architecture of different sizes that can be incorporated in favor of high efficiency video coding (HEVC) benchmark. This formation is optimized in terms of power and area. It is accompanied by a quantization block. Optimized constant matrix multiplication scheme is adapted to implement the I-DCT architectures of different sizes. The power efficient structure for a 2-D DCT module with folding technique is employed for coefficient reusability. It is also shown that this structure can be reusable for different lengths of DCT such as 4, 8, 16, and 32. From simulation and synthesis results, it is observed that the implemented architecture offers less area and power compared to the direct method of implementing conventional architectures. The hardware complexity is also reduced using reusable architectures of I-DCT. This architecture can support ultra high definition frames at very high frame rate, which is very important requirement of HEVC standard.