Python based framework for HDSLs with an underlying formal semantics: (Invited paper)
Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker · 2017
Although Moore's law is slowing down, design productivity is still a big issue in semiconductor industry. Drivers are the trend to 3D integration, the addition of design goals such as ultra-low power and safety, and an increasing number of designs in IoT and automotive areas. EDA tools such as high-level synthesis cover a small design area only. Also, the impact of IP reuse is overestimated since IP integration often requires complex configuration and additional software to be developed. To continuously increase design productivity, Infineon heavily relies on an in-house automation framework that utilizes Python as language for automation and synthesis. It supports (and makes use of) classical HDSLs to describe specific design aspects. Mostly structured specification formalisms such as tables, requirements or diagrams (e.g. SysML subsets) are used. These formalisms can be seen as HDSLs with the additional benefit that they exist as a result of a specification process, i.e. need not be coded explicitly. To be able to deal with several formalisms, Infineon's automation framework follows OMG's MDA vision and utilizes meta-models e.g. for generation of infrastructure code. This work focuses on the aspect of combining DSLs, defining a formal semantic for HDSLs and using this definition to validate the correctness of the mapping of HDSLs to HDLs, an essential pillar to connect HDSLs to today's design flows.