Neural Network Synchronous Binary Counter Using Hybrid Algorithm Training
NXP Semiconductors Noida, India, Ravi Teja Yakkali, N. S. Raghava · International Journal of Image Graphics and Signal Processing · 2017
Information processing using Neural Network Counter can result in faster and accurate computation of data due to their parallel processing, learning and adaptability to various environments.In this paper, a novel 4-Bit Negative Edge Triggered Binary Synchronous Up/Down Counter using Artificial Neural Networks trained with hybrid algorithms is proposed.The Counter was built solely using logic gates and flip flops, and then they are trained using different evolutionary algorithms, with a multi objective fitness function using the back propagation learning.Thus, the device is less prone to error with a very fast convergence rate.The simulation results of proposed hybrid algorithms are compared in terms of network weights, bit-value, percentage error and variance with respect to theoretical outputs which show that the proposed counter has values close to the theoretical outputs.