An approach for efficient realization of multi-operand addition on FPGAs using ternary-adders
Noureddine Chabini, Saïd Belkouch · 2017
Multi-operand addition is found in many real-life applications. Field Programmed Gate Array (FPGA) has emerged as a platform for realizing digital systems. In this paper, we propose an approach for realizing multi-operand addition using ternary-adders on FPGAs. We focus on the case where the operands are of different sizes. The proposed approach reduces the area of the final implementation while reducing its propagation delay.