FPGA implementation of combined AES-128
M. Rajeswara Rao, R. K. Sharma · 2017
This paper is about the implementation of memory less AES with combined architecture for both encryption and decryption processes. An input pin `ErD' makes the architecture to perform encryption/decryption. A key expansion algorithm has made for both encryption and decryption to generate the round keys for both encryption and decryption. Instead of using different hardware for encryption and decryption, a same hardware with a combined architecture of AES can be used in the communication links, such that area and power consumptions will reduce. All the round transformations will be performed in one clock cycle, so that 10 clock cycles are sufficient to complete the encryption/decryption process of AES-128.