3D video coding development based on FPGA platform Xilinx Zynq-7000
Alexander Victor Bukit, Wirawan Wirawan · 2017
Digital video compression techniques have an important role that makes transmission and storage of multimedia content in bandwidth and storage space limited environment efficient. This paper describes 3D video coding using FPGA encoder architecture for newer and more reliable multimedia technologies to drive the industry to improve services in the field of entertainment marketing, to encourage the popularization of 3D video content, supporting devices 3D capabilities, and 3D applications. As a phenomenon that occurs at this time, smartphones, tablets, and other mobile devices has surpassed the value of PC sales. Along with the growing popularity of 3D video and be applied to the mobile device, resulting in the need for storage, data transmission, and display requires an efficient coding. The design is described in VHDL and synthesized to Zynq 7000 AP SoC FPGA. The throughput of the FPGA architecture reaches a processing at 666 MHz, RAM frequency 533 MHz permitting its use in H.265/HEVC standard directed to HDTV. To improve reliability in the process of encoder, one of which can be done by implementing a code HEVC to Zynq 7000 AP SoC.