High throughput design and implementation of SHA-3 hash algorithm
Xufan Wu, Shuguo Li · 2017
In this paper, we propose two different hardware structure of SHA-3 hash algorithm for different width of circuit interface. They both support the four functions SHA3-224/256/384/512 of SHA-3 algorithm. The padding unit of our design is also implemented by hardware instead of software. Besides, a 3-round-in-1 structure is proposed to speed up the throughput of our circuit. We conduct an implementation based in SMIC 65 nm technology, SHA3-224, SHA3-256, SHA3-384 and SHA3-512 achieve the throughput of 65.5 Gbps, 61.8 Gbps, 47.2 Gbps and 32.7 Gbps respectively which are better than the reported designs.