Power mitigation of a heterogeneous multicore architecture by frequency scaling in an OFDM receiver test case
Sajjad Nouri, Jari Nurmi · 2017
In this paper, an integrated self-aware computing model is applied in order to mitigate the power dissipation of a Heterogeneous Multicore Architecture (HMA) used for implementing the Orthogonal Frequency-Division Multiplexing (OFDM) receiver blocks for a proof-of-concept test case. The platform consists of template-based Coarse-Grained Reconfigurable Array (CGRA) devices arranged over a Network-on-Chip (NoC) around a few Reduced Instruction-Set Computing (RISC) cores. The self-aware computing model is executed by the use of Feedback Control System (FCS) which constantly monitors the execution-time of each core and then dynamically scales the operating frequency based on the worst counted execution-time. Therefore, the performance of the overall system will be equalized towards a desired level besides mitigating the power dissipation. Measurement results show that up to 20.2% dynamic power dissipation and 16.8% total power dissipation savings can be obtained for a proof-of-concept test.