Design and Implementation of 8-Bit Low Power Parity Preserving Carry Skip Adder Using Reversible Computing
Ankush Mongia · International Journal of Advanced Science and Technology · 2017
The fundamental operation in most digital circuits is binary addition.It serves as a building block for synthesis all other arithmetic operations.Low-power and high-speed adder cells (like carry skip adder) are used in binary operation based devices.Now the biggest challenge is reduction of adder circuit power consumption and maintaining the high performance in different types of circuit design.Parity preserving is also one of the oldest methods for error recognition in digital systems.In this article 8-bit & modified 8bit design of carry skip adder is proposed.The proposed method uses gates such as ZPLG, LCG, NFT & F2G reversible logic gates as skip logic in the design that leads to decrease in power consumption & quantum cost of the circuit.