Design of garbage free reversible multiplier for low power applications
A. N. Nagamani, Sandeep Kumar, Vinod Kumar Agrawal · 2017
Any signal processing architecture has a multiplier as its pillar. Its computational capabilities depend on the multiplier's performance. Also, low-power designs are the need of next generation processors. Reversible logic is one of the promising future low power technologies. High-speed multiplication can be achieved if the carry-propagation is faster. Digital compressors have less latency in carry-propagation. In this work, we have explored the usage of 4:2 compressors in Wallace multipliers to speed up the multiplication process by reducing the latency of carry-propagation. The proposed reversible multiplier is garbage free design and also optimized in terms of delay and quantum cost with the trade-off in ancillary inputs. The proposed multiplier finds its applications in the design of high-speed, low-power signal processing architectures such as convolution, filtering blocks, FFTs and IFTs.