Multiple reset domains verification using assertion based verification
Islam Ahmed, Khaled Nouh, Amr Abbas · 2017
Current System on Chip (SoC) designs operate in multiple domains such as clock, reset and power domains. This is done to afford various functionalities existing on different IPs that can work in different configurations. Data propagating across multiple reset domains with the absence of correct synchronizers may be corrupted and unreliable. This paper presents an efficient technique to dynamically validate multiple reset domains violations. The proposal is to first automatically model these violations using System Verilog Assertions (SVA), then instrument the design with the generated assertions and then verify the instrumented design using simulation or formal methods to prove existence of these violations. The paper first categorizes 7 types of the possible reset violations, then writes a unique assertion logic for every category that when de-asserted implies a bug. The framework proves effectiveness in finding issues on real designs with multiple resets.