A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM
K. Imamiya, Yoichi Iwata, Y. Sugiura, Hiroshi Nakamura, H. Oodaira, M. Momodomi, Yoshiyuki Ito, T. Watanabe, Hirohiko Araki, K. Narita, Keisuke Masuda, J. Miyamoto · 2002
A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.