UVM-based verification of ECC module for flash memories
Giuseppe Visalli · 2017
In this contribution, we present a coverage driven functional verification environment based on the UVM framework and the System Verilog language to certify the operational correctness of the ECC error management logic used in volatile and nonvolatile memories. We apply this methodology to floatinggate nonvolatile memories for the embedded market, which requires a read error rate of 10-14. The proposed environment achieves the complete validation of ECC features by 80 coverage main points. Additionally, we cover also the error distribution in the cache buffer, on board the memory, which requires additional 240 coverage points. The advantage of code reusability of this kind of verification environment and the wished coverage plan, achieved in few minutes with respect to the exhaustive approach, make easier the application of the proposed solution to any kind of volatile and nonvolatile memories.