Multi Fault Detection and Correction in Fault Tolerance Parallel Fats Using Bch Code
P. Pushpalatha · International Journal for Research in Applied Science and Engineering Technology · 2017
A low complexity and error tolerant design has more demand in the signal processing systems.As technology increases as complexity of circuits also an increase that tends face reliability challenges and creates need for fault-tolerant implementations.Signal processing and communication circuits are affected by soft errors.The complexity increases as protection against soft errors increases in many applications.In communication systems data transfer protection coded with error correction codes (ECCs) has been proposed to efficiently protect data against soft errors.So far it has been evaluated only for single error correction codes.As technology increases multiple bit error are more frequent and thus more advanced protection is needed.In this case we have to implement the fault tolerance in order to preserve the data efficiently.ECCs is the one of the method to detect and correct errors in FFTs.This scheme evaluates protect data using double error correction (DEC) codes.This method allows most efficient protection when there is large number of parallel FFTs present.Results show that this DEC scheme reduces errors effectively and reduce the circuit overheads.