Work-in-progress: REDEFINE – a case for WCET-friendly hardware accelerators for real time applications
Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, François Neumann, Philippe Baufreton · 2017
REDEFINE is a distributed dynamic dataow architecture, designed for exploiting parallelism at various granularities as an embedded system-on-chip (SoC). is paper dwells on the exibility of REDEFINE architecture and its execution model in accelerating real-time applications coupled with a WCET analyzer that computes execution time bounds of real time applications.