Latest generation interconnect technologies in APEnet+ networking infrastructure
Roberto Ammendola, A. Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, A. Lonardo, Michele Vittorio Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Davide Rossetti, Francesco Simula, P. Vicini · Journal of Physics Conference Series · 2017
In this paper we present the status of the 3 rd generation design of the APEnet board (V5) built upon the 28nm Altera Stratix V FPGA; it features a PCIe Gen3 x8 interface and enhanced embedded transceivers with a maximum capability of 12.5Gbps each. The network architecture is designed in accordance to the Remote DMA paradigm. The APEnet+ V5 prototype is built upon the Stratix V DevKit with the addition of a proprietary, third party IP core implementing multi-DMA engines. Support for zero-copy communication is assured by the possibility of DMA-accessing either host and GPU memory, offloading the CPU from the chore of data copying. The current implementation plateaus to a bandwidth for memory read of 4.8GB/s. Here we describe the hardware optimization to the memory write process which relies on the use of two independent DMA engines and an improved TLB.