Evaluation of an Overlay architecture in FPGAs withBig Data and Scientific Kernels
Konstantinos Gkougkoulias · 2017
In recent years due to the slow down of Moores Law and Dennard Scaling, alternative architectures have started to been used instead of plain CPU implementations. One solution is FPGAs but the problem with them is high the high effort and specialization required for implementation. Furthermore an implementation is specific to a certain algorithm and cannot be used for any other algorithm even if is it slightly different. Also designing for FPGAs is acomputationally intensive task as the whole design after simulation has to be synthesized and then placed and routed(PaR) for a particular FPGA every time the design changes slightly. This process of mapping the design can take hours or even days to compute for large designs. In recent years developments in High Level Synthesis (HLS) and OpenCL has made the whole process of designing for FPGAs an easier task. But this solution is not without problems either as the algorithm has to be still implemented for a specific FPGA device. A solutionto the FPGA synthesis and PaR problem has recently been proposed at the name of FPGA Overlay Architectures. The core concept of this idea to abstract the FPGA create a virtual FPGA on top of the real one in order to help with configuration time. Our results show that indeed reconfiguration can be achieved only in 11.9us, at the usage of 10.5x more LUTs and a drop in frequency for the chosen architecture but there is room for improvement optimizing the interconnect network.