Design of streaming deblocking filter for HEVC decoder
Rangababu Peesapati, Sonketa Das, Swamy Baldev, Shaik Rafi Ahamed · IEEE Transactions on Consumer Electronics · 2017
This paper presents a hardware architecture using mixed pipelined and parallel processing for Deblocking Filter (DBF) in High Efficiency Video Coding (HEVC) standard. The objective of the proposed work is to achieve low latency architecture for the DBF stage in HEVC. The work investigates the processing of different sizes of coding unit (CU) by partitioning each frame into blocks of different sizes (8x8, 16x16, 32x32 and 64x64). In order to execute filtering on multiple edges simultaneously without affecting the neighboring blocks, the block sizes have been increased to 12x12, 20x20, 36x36 and 68x68 with respect to aforementioned sizes. Moreover, the horizontal and vertical filtering of the frame is performed in a streaming fashion. The proposed work is implemented on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms. The results are compared with state-of-the-art literature and conclude that the proposed work with 36x36 block size architecture is suitable for ultra-high definition (UHD) resolution based consumer applications due to its occupancy of moderate amount of resources and higher processing speed.