Clustered voltage scaling design technique for low-power hashing unit
Andrey V. Korshunov, Волобуев Павел Сергеевич, Alexander L. Stempkovsky, S. V. Gavrilov, Daria A. Ryzhova · 2017
This work is focused on a technique providing the integration of the method of clustered voltage scaling (CVS) in the digital design flow. The efficiency of this technique in the case of a hashing unit IP-block is considered. In order to reduce the power consumption special hash algorithms (NH, PH) in combination with the CVS approach were proposed. For the implementation of the CVS technique a number of standard cells have been developed: level shifters and flip-flops with level conversion. The simulation results have showed that developed hashing unit with the CVS technique allows - decreasing power consumption on average by 12% with area penalty about 3% and without timing degradation.