Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering
Arvind Singh, Monodeep Kar, Sanu K. Mathew, Anand Prem Rajan, Vivek K. De, Saibal Mukhopadhyay · 2017
The paper demonstrates improved power side channel attack (PSCA) resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) attacks even after 500,000 encryption traces.