Design of R3TOS based reliable low power network on chip
N Poornima, Gopalakrishnan Seetharaman, Tughrul Arsalan, THAMMAMPATTI NATARAJAN PRABAKAR, M. Vijaya Santhi · 2017
In this paper, design of a novel Network on Chip (NoC) structure and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) are presented. NoC has been recently identified as a scalable communication paradigm to avoid the communication bottleneck in bus based communications. Dynamically Reconfigurable Field Programmable Gate Array (FPGA)s are particularly suited for applications that can be broken into a number of different tasks. An interface is required to communicate between the different tasks. Hence, R3TOS can be used among other functionalities to manage the interface between different tasks on FPGA. Secondly, the speed is increased by introducing a novel architecture for removing the head of line blocking by designing a control unit. This architecture also removes the need for tail flit by including the information about number of data flits in the head flit. Third, the reliability factor is improved with incorporation of error Detection and Correction techniques into NoC structure. For verification, all the three schemes are implemented in Zync 7000 series. From the implementation results, it is verified that, the performance of the proposed NoC results in high speed and low power consumption compared to generic router.