Exploration of High‐level Synthesis Technique
Chao Li, Souleymane Balla-Arabé, Fan Yang‐Song · 2017
High-level synthesis (HLS) is a promising technique to increase FPGA development productivity. It allows users to reap the benefits of hardware implementation directly from the software source code specified by C-like languages. This chapter explores the synthesis process of Vivado_HLS, one of the leading HLS tools. HLS is also called C synthesis or electronic system level synthesis. C is a structured programming language that consists of sequential, selectional and repetitional statements, so Vivado_HLS begins the synthesis process with the control and datapath extraction including control behavior extraction, operations extraction and control and datapath creation. The chapter expresses that the HLS process is highly available to automate the C-to-RTL conversion. Depending on different fitness functions, designers can customize different prediction strategies. Kubelka-Munk genetic algorithm (KMGA) terminates the evolution process by defining an iteration number which corresponds to the convergence of the population.