Improving Energy Efficiency in Memory-constrained Applications Using Core-specific Power Control
Sridutt Bhalachandra, Allan Porterfield, Stephen L. Olivier, Jan F. Prins, Robert J. Fowler · 2017
Power is increasingly the limiting factor in High Performance Computing (HPC) at Exascale and will continue to influence future advancements in supercomputing. Recent processors equipped with on-board hardware counters allow real time monitoring of operating conditions such as energy and temperature, in addition to performance measures such as instructions retired and memory accesses. An experimental memory study presented on modern CPU architectures, Intel Sandybridge and Haswell, identifies a metric, TORo_core, that detects bandwidth saturation and increased latency.