Exploring 3D Network-on-Chip Architectures and Challenges
Sapna Tyagi, Piyush Maheshwari, Amit Agarwal, Vinay Avasthi · 2017
Network-on-Chip (NoC) is a nascent approach for reducing the communication bottleneck of multicore System-on-Chip (SoC). As the number of cores are increasing on SoC due to high performance demand of the consumer electronics and processing systems like servers, the low power and low latency NoC is required. Topologies are one of the most important parts of a NoC design, with considering the performance parameter as a constraint. The important parameters of networks-on-chip are latency, throughput, injection rate and average number of hops etc. In our work, various existing 3D NoC architectures and their performance are studied and presented. The basic concepts of NoC and motivation for 3D NoC and its advantages over 2D NoC are also focused in this paper. We have also investigated and demonstrated 144 nodes and 256 nodes 3D mesh architecture in terms of the latency, throughput and injection rate.