Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache
Tyler Stocksdale, Mu-Tien Chang, Hongzhong Zheng, Frank Mueller · 2017
Due to the recent growth in the number of on-chip cores available in today's multi-core processors, there is an increased demand for memory bandwidth and capacity. However, off-chip DRAM is not scaling at the rate necessary for the growth in number of on-chip cores. Stacked DRAM last-level caches have been proposed to alleviate these bandwidth constraints, however, many of these ideas are not practical for real systems, or may not take advantage of the features available in today's stacked DRAM variants.