High speed efficient advanced encryption standard implementation
Soufiane Oukili, Seddik Bri · 2017
Cryptography is the science of secure data transmission through an insecure channel. Advanced Encryption Standard (AES) is the most widely and secure symmetric key cryptographic algorithm today. The complexity of AES is dominated by the substitution box (S-box) transformation which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. In this article, we present high speed efficient AES architecture. We have used pipeline technique to allow a parallel processing in order to obtain high throughput. In addition, 5-stage pipeline S-box design using combinational logic is introduced to increase the speed and the maximum operating frequency. Furthermore, pipeline registers are inserted in optimal placements to reduce the occupied area and reach an efficient architecture. The proposed design had been successfully implemented in virtex-6 FPGA device using Xilinx ISE 14.7. It achieves a throughput of 79Gbps and occupied 4830 slices memory.