Latency reduction of fault-tolerant NoCs by employing multiple paths
Ronaldo T. P. Milfont, Rafael Goncalves Mota, Joao Marcelo Ferreira, Paulo César Cortez, Cesar Augusto Missio Marcon, Daniel Alencar Barros Tavares, Jarbas Silveira · 2017
Digital circuit technologies at nanoscale levels increase the likelihood of permanent, transient and intermittent faults. As a result, the demand for fault tolerance strategies is the main subject of many types of research targeting System-on-Chip (SoC) designs. In particular, retransmission mechanisms are one of the most used solutions in the Network-on-Chip (NoC) operation, but these mechanisms introduce delays in the packet latency. This paper proposes the use of multiple paths as a way to reduce latency due to the impact of retransmissions in critical systems, i.e., where latency is a critical issue. The experimental results show that the use of multiple paths, minimal or not, enable to decrease the impact caused by retransmissions in 25% and 20% of the average packet latency for 22 and 65 nm CMOS technologies, respectively. Moreover, the proposed technique has a low impact on the average latency of the entire network and can contribute to a greater adaptability of faults on links.