Layered T comparator design using quantum-dot cellular automata
Soudip Sinha Roy, Chiradeep Mukherjee, Saradindu Panda, Asish Kumar Mukhopadhyay, Bansibadan Maji · 2017 Devices for Integrated Circuit (DevIC) · 2017
Comparator is crucial block in Central Processing Unit especially in the process of “Data Searching-Sorting” where huge amount of data needs to be searched during the Database Management operations. In this work, the logic design of 1-bit Quantum Cellular Automata (QCA) comparator has been proposed using the Layered-T AND and OR Gates. The proposed comparator layout needs 9.02% less effective area compared to the best reported design so far. The effect of cell misplacements on the proposed layout is thoroughly investigated. Moreover, the other QCA design metrics such as O-Cost, CostI are calculated for the proposed 1-bit Layered T Comparator circuit. The functionality of the proposed circuit is verified by computer aided design tool QCADesigner 2.0.3.