ASIC implementation of distributed arithmetic in adaptive FIR filter
S. Raghunadha Reddy, P. Jayakrishnan · 2017
This paper presents a new architecture for high performance and low power implementation of FIR filter by using Distributed Arithmetic. The speed of the architecture increased because of parallel implementation of coefficient updating and the filtering. The throughput is increased when compare with the conventional DA based adaptive FIR filter because of replacing carry save accumulator instead of the normal accumulator. By using this architecture, we can reduce the number of adders to design the DA based architecture. In this paper, we calculate the area delay product (ADP), area and power for different filter lengths.