The application of multi-valued logic to the implementation of Residue Number System Hardware.
Peter D. Bird · Scholarship at UWindsor (University of Windsor) · 1987
techn iqu es was c a r r ie d o u t.Based on the fin d in g s from th is s u rv ey, and on the r e s t r i c t i o n s imposed by the IC f a b r i c a t i o n process th a t was a v a i 1a b l e , a te rn a r y v o lta g e mode lo g ic system was chosen fo r a more d e t a i l e d a n a ly s is .To augment the da ta o b ta in e d from the l i t e r a t u r e s u rv ey, th re e RNS adders were d esig ned , two using stand ard b in a ry lo g ic and one using the te rn a r y system m entioned above.These designs fo llo w e d the same b asic s t r u c t u r e , each comprised a ROM, decoders and la tc h e s .The b e t t e r of the two b in a ry designs was a b le to produce the sum of two f i v e b i t numbers, using modular a d d it i o n , in 24ns.The te r n a r y design can sum two th re e t r i t numbers in 52ns.The im p ressive speed perform ance of these c i r c u i t s is due to the p ip e lin e d s t r u c t u r e of the d esig ns.From these design e f f o r t s , and those of the authors r e f e r r e d to in the l i t e r a t u r e s u rv e y , i t was p o s s ib le to compare the a re a , speed and power consumption of the m u l t i v a lu e d and b in a ry approaches to c i r c u i t d e s ig n .In g e n e r a l, i t can be s ta te d th a t m u lt i-v a lu e d designs are slower and consume more power than the co rrespon din g b in a r y d esig ns.For many d e sig n s, however, e s p e c ia ll y those based c h i e f l y on ROMs, the m u lt i-v a lu e d approach can produce s i g n i f i c a n t area s a v in g s .