Technical memorandum. Systolic array implementation of a decimator and an interpolator
T.S. Okullo-Oballa, Hon Keung Kwan · IEE Proceedings E Computers and Digital Techniques · 1988
Two systolic arrays for the VLSI implementation of the decimation and interpolating structures advanced by Valenzuela and Constantinides are presented. Each of the resultant arrays consists of basic cells characterised by nearest neighbour interconnections and high throughput rate.