Low power Viterbi decoder design based on reversible logic gates
K B Naveen, G S Puneeth, M N Sree Rangaraju · 2017
In recent trends of VLSI technology the reversible logic has became the major area of research in optimization of area, power and speed constraints. The reversible logic has equal number of inputs and outputs. In wireless communications Viterbi algorithm is employed to have minimal number of communication channels. The Viterbi decoder design at 65nm technology using reversible logic has made an attempt for optimizing power, area and delay with increased efficiency.