Pipelining a triggered processing element
Thomas J. Repetti, Joao Pedro Cerqueira, Martha A. Kim, Mingoo Seok · 2017
Programmable spatial architectures composed of ensembles of autonomous fixed-ISA processing elements offer a compelling design point between the flexibility of an FPGA and the compute density of a GPU or shared-memory many-core. The design regularity of spatial architectures demands examination of the processing element microarchitecture early in the design process to optimize overall efficiency.