Implementation of multi - priority and variable - length DRRM scheduling algorithm based on FPGA
Hui Xu, Xue Sun, Suzhi Cao, Yueying Zhan · AIP conference proceedings · 2017
In order to improve the bandwidth utilization of the switch fabric, reduce the complexity of the arbitration module and reduce the processing of the packet, the existing DRRM scheduling algorithm is improved to support the variable-length cell scheduling and provide multi-priority level support. We use Xilinx xc7k325t FPGA to achieve a 16×16 ports data exchange structure, providing six different priorities to support the complete variable-length cells directly involved in scheduling.