A FSM based approach for efficient implementation of K-means algorithm
Rahul Ratnakumar, Satyasai Jagannath Nanda · 2016
After Fifty years of it's existence the K-means clustering is still popular among researchers due to lower computational complexity. Real time embedded applications require hardwiring of unsupervised learning algorithms like K-means within System-on-Chip for prompt processing in applications like image segmentation, pattern classification, speech recognition etc. This requirement is a must while analyzing Big Datasets. In this manuscript a FSM based architecture is developed for the efficient implementation of K-means algorithm. The proposed architecture has lower computational requirement due to the introduction of concepts like simplified Convergence Checker as well as Fibonacci linear feedback shift register for centroid initialization. To reduce hardware further, Manhattan distance is used as the distance metric instead of the conventional Euclidean distance. Benchmark IRIS flower dataset is used for testing the clustering performance of the proposed architecture. Results obtained after synthesis in Xilinx FPGA Artix7, reveals that the hardware performance is better than previous works, with respect to power (82mW), number of gates, area etc. and has good system clock frequency of 162MHz (6.1592ns), without using any DSP Blocks.