Low-power Parallel Data Processing Using Computation Reuse
Bita Dabiri, Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi · 2017
A wide range of real-world applications, including DSP, deep learning, multimedia, and scientific algorithms generally include fixed-point and floating-point arithmetic operations and trigonometric functions which have long latency and high power usage. In this paper, we propose a computation reuse mechanism for multicore processors that reuses the results of an arithmetic operation for subsequent operations with (approximately) the same operands. It adds a small so-called result cache to every functional unit that keeps a few recent operands and their results to detect repetitive operands and reuse the results. Taking advantage of the value locality inherent in many real-world applications, our architecture relies on a multi-stage interconnection network to distribute input data elements across the cores of a multi-core processor in such a way that the data locality of each core is increased. This way, each core has higher computation reuse rate that translates to more power consumption reduction. Experimental results show that the proposed mechanism increases the result cache hit rate, which leads to a significant reduction in power consumption of arithmetic operations.