Reducing FIFO buffer power using architectural alternatives at RTL
Ashish Kumar Sharma, Ruby Ansar, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi · 2016
NoC has a significant impact on the power, area and performance of multi-core architectures. The contribution of NoC in the total power budget of a CMP is approximately 30 to 40% [1], and the input buffers of router consume most of it. Therefore, the designers need to design a low power communication architecture of NoC by reducing the power consumption of buffers. In the existing techniques, virtual channel buffer power has been optimized by employing buffer sharing, power gating with flexible virtual channels and Dynamic Voltage Frequency Scaling (DVFS). In this paper, we have proposed a) Routing Logic enabled clock gating at input channel buffers b) Further, we applied the clock gating on FPGA slices on our proposed design. Our approach provides a significant improvement in FIFO buffer power in 2D NoC as the FIFO power is optimized by 10.70%. Furthermore, 37% of improvement in dynamic power has been achieved by applying clock gating on slices and block RAM on our proposed routing logic enabled input channel buffers clock gating technique.