SEU mitigation of Rad-Tolerant Xilinx FPGA using external scrubbing for geostationary mission
Mahesh Kumar, Durga Digdarsini, Neeraj Kumar Misra, Tulchhi Ram · 2017
This paper presents the design and implementation of an effective Single Event Upset (SEU) mitigation technique for radtolerant Xilinx virtex-4xqr4vsx55FPGA used in Digital Bandwidth Efficient Filter (DBEF) subsystem for a Geostationary mission. The Single Event Effects (SEE) on the virtex-4FPGA are minimized using an external scrubbing engine, which is implemented using rad-hard RTSX32SU-CQ84 Actel FPGA. The availability and reliability analysis shows an optimum window for performing scrubbing function in Geo-stationary earth orbit.